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Center for Adaptive Supercomputing - Multithreaded Architectures

Workshop on Parallel Algorithms and Software for Analysis of Massive Graphs (ParGraph)


Held in conjunction with:

Organizers: Ümit Çatalyürek (The Ohio State University) and Mahantesh Halappanavar (Pacific Northwest National Laboratory)

Workshop Chair: Alex Pothen, Professor of Computer Science, Purdue University, and Director of CSCAPES Institute


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2:00 – 3:00 Keynote
“Opportunities and Challenges in Massive Data-Intensive Computing”
David Bader , Georgia Institute of Technology
3:00 – 3:30 Invited Talk
 “Parallel and Distributed Algorithms for Graph Similarity Computations”
Giorgos Kollias, Karthik Kambatla, and Ananth Grama
 Center for Science of Information, Purdue University
3:30 – 4:00 Coffee Break
4:00 – 4:30 “Parallelization of MIRA Whole Genome and EST Sequence Assembler”
Abhishek Biswas, Desh Ranjan, and Mohammad Zubair
Department of Computer Science, Old Dominion University
4:30 – 5:00 “An Efficient MapReduce Algorithm for Parallelizing Large-scale Graph Clustering”
Inna Rytsareva and Ananth Kalyanaraman
School of Electrical Engineering and Computer Science, Washington State University
5:00 – 5:30 “Performance Analysis of Vertex-centric Graph Algorithms on the Azure Cloud Platform”
Mark Redekopp, Yogesh Simmhan and Viktor K. Prasanna
Viterbi School of Engineering, University of Southern California
5:30 – 6:00 Invited Talk
"Parallel Graph Algorithmic Challenges in High-Throughput Sequence Assembly" 
Srinivas Aluru
, Iowa State University and IIT Bombay

Call for Papers:

Combinatorial algorithms play an important enabling role in several areas of science and engineering. Many combinatorial algorithms, graph algorithms in particular, are characterized by irregular data-access patterns that make efficient implementation on traditional high-performance computing platforms challenging. Architectural features, algorithmic design and software engineering techniques, and characteristics of the input collectively determine the performance of these algorithms. In addition, runtime support for irregular applications, programming models (e.g., partitioned global address space (PGAS), bulk-synchronous processing (BSP), active messages), and the emergence of hybrid manycore platforms deserve attention. With this workshop we facilitate a forum to bring together diverse researchers interested in combinatorial (graph) algorithms, data intensive applications involving them, and parallel computing.

We seek submissions on broad topics of interest as listed below, but not limited to this:

  • Theory and Algorithms:
    • Combinatorial (graph) algorithms and libraries
    • Algorithms for analysis of large complex networks (social network analysis)
    • Approximation algorithms and bounds
  • Design and performance evaluation of algorithms on:
    • Traditional architectures: massively parallel distributed-memory systems (IBM BlueGene, Cray XT), shared-memory multicore systems (Intel, AMD)
    • Nontraditional architectures: massively multithreaded architectures (Cray XMT), manycore and tiled platforms (Nvidia, AMD, Tilera)
  • Applications:
    • Combinatorial Scientific Computing o Data Mining; Graph Mining;Machine Learning
    • Bioinformatics; Information (Cyber) security; Mobile computing
    • Visual Analytics; Graph Visualization
  • Programming paradigms and runtime support for irregular applications

Submission Details:

We seek high quality manuscripts detailing creative and original research. The manuscripts should not be currently under review at any other venue. Please do not exceed eight (8) pages following the HiPC paper formatting guidelines (also attached below). We will not consider submissions that deviate significantly from the above guidelines. We guarantee at least three independent reviews for all submitted papers. Workshop proceedings will be published as a separate CDROM Proceedings by HiPC. Hardcopy proceedings will not be provided. HiPC is sponsored by ACM and IEEE.

Please submit your work using EasyChair. Do not use the HiPC Conference submission system. Please contact the organizers if you have any questions, send email to the organizers.

In addition to regular papers, we also encourage shorter 4 or 6-page papers describing work-in-progress.

Authors of selected papers from the workshop will be invited to submit an extended version of their manuscript to the Special Issue on: "Architectures and Algorithms for Irregular Applications" of the International Journal of High Performance Computing and Networking .

Important Dates:

  • October 7, 2011: Submission of manuscripts - deadline extended!
  • October 15, 2011: Notification of decision
  • November 07, 2011: Submission of camera-ready papers
  • December 18, 2011: Workshop


At least one author should register for the workshop and present the work in person. Workshop attendance will be included as part of the regular HiPC conference registration. HiPC will provide breakfast and lunch to the workshop attendees.

Confirmed Keynote Speaker:

  • David Bader, Professor, School of Computational Science and Engineering, College of Computing, Georgia Institute of Technology, and Executive Director for High Performance Computing.

Program Committee:

  • Sanjukta Bhowmick, University of Nebraska, Omaha
  • Sutanay Choudhury, Pacific Northwest National Laboratory
  • Edmond Chow, Georgia Institute of Technology
  • Jonathan Cohen, nVIDIA
  • Guojing Cong, IBM T. J. Watson Research Center, Yorktown Heights
  • John Feo, Pacific Northwest National Laboratory
  • Anshul Gupta, IBM T. J. Watson Research Center, Yorktown Heights
  • Bruce Hendrickson, Sandia National Laboratories
  • Kamesh Madduri, Lawrence Berkeley National Laboratory
  • Fredrik Manne, University of Bergen
  • Oreste Villa, Pacific Northwest National Laboratory
  • Pak Chung Wong, Pacific Northwest National Laboratory
  • Andy Yoo, Lawrence Livermore National Laboratory

HiPC Manuscript Guidelines:

Submitted manuscripts should be structured as technical papers and may not exceed 10 letter size (8.5 x 11) pages including figures, tables and references using the IEEE format for conference proceedings (print area of 6-1/2 inches (16.51 cm) wide by 8-7/8 inches (22.51 cm) high, two-column format with columns 3-1/16 inches (7.85 cm) wide with a 3/8 inch (0.81 cm) space between them, single-spaced 10-point Times fully justified text).

Submissions not conforming to these guidelines may be returned without review. Authors should submit the manuscript in PDF format and make sure that the file will print on a printer that uses letter size (8.5 x 11) paper. The official language of the meeting is English. Manuscript submission procedures will then be available over the Web at Electronic submissions must be in the form of a readable PDF file. Manuscripts should demonstrate current research in any area of high performance computing. All manuscripts will be reviewed and will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference attendees.

Submitted papers must represent original unpublished research that is not currently under review for any other conference or journal. Papers not following these guidelines will be rejected without review and further action may be taken, including (but not limited to) notifications sent to the heads of the institutions of the authors and sponsors of the conference. Submissions received after the due date, exceeding length limit, or not appropriately structured may also not be considered.


Research and Development